1. Field Of The Invention
This invention relates to flash electrically-erasable programmable read-only memory (flash EEPROM) memory arrays and, more particularly, to methods and apparatus for allowing the reading from or writing to such a memory array and the verification of programming and erase operations in such an array on either an eight or a sixteen bit basis.
2. History Of The Prior Art
Modern computer systems make extensive use of long term memory. One form of long term storage used in computers is flash EEPROM. A flash EEPROM memory array is an EPROM memory array which may be electrically erased in place and reprogrammed. A flash EEPROM memory array includes a large plurality of floating-gate field effect transistors arranged as memory cells in typical row and column fashion with circuitry for accessing the individual cells and placing the memory transistors of those cells in one of two memory conditions. A flash memory cell, like a typical EPROM cell retains information when power is removed.
Flash EEPROM memory has a number of characteristics which adapt it to use as long term memory. It is light in weight, occupies very little space, and consumes less power than electro-mechanical disk drives. More importantly, it is especially rugged. It will withstand without adverse effects repeated drops each of which would destroy a typical electro-mechanical hard disk.
A difficulty with flash EEPROM, however, is that it is very slow to erase. Flash EEPROM is erased by applying a high voltage simultaneously to the source terminals of all of the transistors (cells) used in the memory. Because these source terminals are all connected to one another by metallic busing in the array, the entire array must be erased at once. If any valid data remains in the array, it must be saved before erasure occurs and rewritten to the array after the array has been completely erased.
An arrangement has been devised to accomplish the programming, reading, and erasing of flash EEPROM memory arrays. This arrangement includes a command state machine which provides a command interface between the host computer and the flash EEPROM memory array. The command state machine receives and controls all instructions and data sent by the host computer to the flash memory array and all data and signals provided by the flash memory array for the host. The command state machine sequences the various information to and from the host using a write state machine to program and erase so that the writing to and reading from the array occurs in proper order. Because it sits between the host and the memory array and controls all information passed therebetween, the command state machine is able to control the erasure process so that the external host which is writing to and receiving information from the flash array is typically not aware that an erasure is taking place even though the erasure requires one or two seconds and includes a verification of the accuracy of the erasure. In order to accomplish this, the command state machine has the ability to suspend the erasure process in order to allow various commands from the host to be implemented. The details of the command state machine and the write state machine are described in U.S. patent application Ser. No. 07/655,643, entitled Command State Machine, Fandrich et al, filed Feb. 11, 1991, and assigned to the assignee of the present invention, and in U.S. patent application Ser. No. 07/654,375, entitled Circuitry and Method For Programming and Erasing A Non-volatile Semiconductor Memory, Kynett et al, filed Feb. 11, 1991, and assigned to the assignee of the present invention.
Flash EEPROM memory arrays, like other forms of long term memory, must read and write data which a host may desire or furnish in either byte or word form. The first flash EEPROM memory arrays carried out read and write operations involving only eight bit values and simply took longer to store and read word length values. More recently, arrays which may be written or read in sixteen bit quantities have been designed. With these arrays it is desirable to be able to read and write data, in not only in sixteen bit quantities, but also in eight bit quantities which may be either the high or low byte of a sixteen bit word.
Moreover, in order to complete the erase process of those sixteen bit arrays as fast as possible, it is desirable to verify the accuracy of the erasure sixteen bits at a time. However, because the erasure process takes so long in flash EEPROM memory arrays, it must be suspended frequently so that data may be read from the flash EEPROM memory. Often, only eight bits of data are to be read by the host computer. Consequently, it is desirable when erasing in the sixteen bit mode to be able to accomplish eight bit read operations of both the upper and lower eight bytes of words stored in the array.
Another especially valuable facility of the control circuitry of the eight bit flash EEPROM memory array (which includes the command and write state machines) is the ability to assure that any data written to the array is written correctly and that erasure has been accomplished successfully. In order to verify this, any data written to the array is latched and compared to the data which is expected to be written. It is desirable that this same facility be available to the array whether the data is being written in eight or sixteen bit quantities and whether eight bit quantities of data are written to either the high or the low order byte positions.